Abstract is missing.
- Fast and area efficient adder for wide data in recent Xilinx FPGAsPetter Kallstrom, Oscar Gustafsson. 1-4 [doi]
- Modeling considerations for the hardware-software co-design of flexible modern wireless transceiversBenjamin Drozdenko, Matthew Zimmermann, Tuan Dao, Kaushik R. Chowdhury, Miriam Leeser. 1-4 [doi]
- Controller architecture for low-latency access to phase-change memory in OpenPOWER systemsAntonios Prodromakis, Nikolaos Papandreou, Eleni Bougioukou, U. Egger, N. Toulgaridis, Theodore Antonakopoulos, Haralampos Pozidis, Evangelos Eleftheriou. 1-4 [doi]
- Model-based optimization of High Level Synthesis directivesCharles Lo, Paul Chow. 1-10 [doi]
- Multi-core for K-means clustering on FPGAJose Canilho, Mário P. Véstias, Horácio C. Neto. 1-4 [doi]
- An implementation method of the box filter on FPGASichao Wang, Tsutomu Maruyama. 1-8 [doi]
- LYNX: CAD for FPGA-based networks-on-chipMohamed S. Abdelfattah, Vaughn Betz. 1-10 [doi]
- Efficient processing of phased array radar in sense and avoid application using heterogeneous computingLuke Newmeyer, Doran Wilde, Brent E. Nelson, Michael J. Wirthlin. 1-8 [doi]
- Automated bug detection for pointers and memory accesses in High-Level Synthesis compilersPietro Fezzardi, Fabrizio Ferrandi. 1-9 [doi]
- Improved resource sharing for FPGA DSP blocksBajaj Ronak, Suhaib A. Fahmy. 1-4 [doi]
- Boosting convergence of timing closure using feature selection in a Learning-driven approachQue Yanghua, Harnhua Ng, Nachiket Kapre. 1-9 [doi]
- Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletonsSidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket Kapre. 1-4 [doi]
- Dimensionality reduction of hyperspectral images using reconfigurable hardwareDaniel Fenzandez, Carlos González, Daniel Mozos. 1-2 [doi]
- Survey of domain-specific languages for FPGA computingNachiket Kapre, Samuel Bayliss. 1-12 [doi]
- Ouessant: Microcontroller approach for flexible accelerator integration and control in System-on-ChipPierre-Henri Horrein, Benoit Porteboeuf, Andre Lalevee. 1-4 [doi]
- SoCLog: A real-time, automatically generated logging and profiling mechanism for FPGA-based Systems On ChipIoannis Parnassos, Panagiotis Skrimponis, Georgios Zindros, Nikolaos Bellas. 1-4 [doi]
- Relational query processing on OpenCL-based FPGAsZe-ke Wang, Johns Paul, Hui Yan Cheah, Bingsheng He, Wei Zhang. 1-10 [doi]
- Accelerating recurrent neural networks in analytics servers: Comparison of FPGA, CPU, GPU, and ASICEriko Nurvitadhi, Jaewoong Sim, David Sheffield, Asit K. Mishra, Srivatsan Krishnan, Debbie Marr. 1-4 [doi]
- High-speed PCAP configuration scrubbing on Zynq-7000 All Programmable SoCsAaron Stoddard, Ammon Gruwell, Peter Zabriskie, Michael J. Wirthlin. 1-8 [doi]
- Chaotic architectures for secure free-space optical communicationEsam El-Araby, Nader M. Namazi. 1-5 [doi]
- Semi-dense SLAM on an FPGA SoCKonstantinos Boikos, Christos-Savvas Bouganis. 1-4 [doi]
- Hardware acceleration of a software-based VPNFurkan Turan, Ruan de Clercq, Pieter Maene, Oscar Reparaz, Ingrid Verbauwhede. 1-9 [doi]
- Energy-efficient stochastic matrix function estimator for graph analytics on FPGAHeiner Giefers, Peter W. J. Staar, Raphael Polig. 1-9 [doi]
- A partial reconfiguration controller for Altera Stratix V FPGAsZhenzhong Xiao, Dirk Koch, Mikel Luján. 1-4 [doi]
- Memory efficient and high performance key-value store on FPGA using Cuckoo hashingWei Liang, Wenbo Yin, Ping Kang, Lingli Wang. 1-4 [doi]
- Optimal random sampling based path planning on FPGAsSize Xiao, Adam Postula, Neil W. Bergmann. 1-2 [doi]
- Demonstration of a context-switch method for heterogeneous reconfigurable systemsArief Wicaksana, Alban Bourge, Olivier Muller, Frédéric Rousseau. 1 [doi]
- Overcoming resource underutilization in spatial CNN acceleratorsYongming Shen, Michael Ferdman, Peter A. Milder. 1-4 [doi]
- ParaFRo: A hybrid parallel FPGA router using fine grained synchronization and partitioningChin Hau Hoo, Yajun Ha, Akash Kumar 0001. 1-11 [doi]
- Accelerating particle identification for high-speed data-filtering using OpenCL on FPGAs and other architecturesSrikanth Sridharan, Paolo Durante, Christian Faerber, Niko Neufeld. 1-7 [doi]
- A runtime reconfigurable FPGA-based microphone array for sound source localizationBruno da Silva, Laurent Segers, An Braeken, Abdellah Touhafi. 1 [doi]
- A high performance FPGA-based accelerator for large-scale convolutional neural networksHuimin Li, Xitian Fan, Li Jiao, Wei Cao, Xuegong Zhou, Lingli Wang. 1-9 [doi]
- An investigation into a circuit based supply chain analyzer for FPGAsJacob Couch, John Arkoian. 1-9 [doi]
- Designing a virtual runtime for FPGA accelerators in the cloudMikhail Asiatici, Nithin George, Kizheppatt Vipin, Suhaib A. Fahmy, Paolo Ienne. 1-2 [doi]
- Runtime-quality tradeoff in partitioning based multithreaded packingDries Vercruyce, Elias Vansteenkiste, Dirk Stroobandt. 1-9 [doi]
- A highly-dense mixed grained reconfigurable architecture with overlay crossbar interconnect using via-switchJunshi Hotate, Takashi Kishimoto, Toshiki Higashi, Hiroyuki Ochi, Ryutaro Doi, Munehiro Tada, Tadahiko Sugibayashi, Kazutoshi Wakabayashi, Hidetoshi Onodera, Yukio Mitsuyama, Masanori Hashimoto. 1-4 [doi]
- Automated extra pipeline analysis of applications mapped to Xilinx UltraScale+ FPGAsIlya Ganusov, Henri Fraisse, Aaron Ng, Rafael Trapani Possignolo, Sabya Das. 1-10 [doi]
- Low-latency TCP/IP stack for data center applicationsDavid Sidler, Zsolt István, Gustavo Alonso. 1-4 [doi]
- An evaluation on the accuracy of the minimum width transistor area models in ranking the layout area of FPGA architecturesFarheen Fatima Khan, Andy Ye. 1-11 [doi]
- Towards an all-digital antenna array transmitterDaniel C. Dinis, Rui Fiel Cordeiro, Arnaldo S. R. Oliveira, José M. N. Vieira. 1-2 [doi]
- Single-FPGA 3D ultrasound beamformerA. C. Yuzuguler, W. Simon, A. Ibrahim, Federico Angiolini, M. Arditi, J. P. Thiran, Giovanni De Micheli. 1 [doi]
- FPGA-based accelerator design from a domain-specific languageM. Akif Ozkan, Oliver Reiche, Frank Hannig, Jürgen Teich. 1-9 [doi]
- SoC and FPGA oriented high-quality stereo vision systemYanzhe Li, Kai Huang, Luc Claesen. 1-4 [doi]
- Configurable and scalable belief propagation accelerator for computer visionJungwook Choi, Rob A. Rutenbar. 1-4 [doi]
- Efficient and reliable High-Level Synthesis Design Space Explorer for FPGAsDong Liu, Benjamin Carrión Schäfer. 1-8 [doi]
- Optimising Sparse Matrix Vector multiplication for large scale FEM problems on FPGAPaul Grigoras, Pavel Burovskiy, Wayne Luk, Spencer J. Sherwin. 1-9 [doi]
- Efficient sum of absolute difference computation on FPGAsMartin Kumm, Marco Kleinlein, Peter Zipf. 1-4 [doi]
- High-level synthesis for medical image processing on Systems on Chip: A case studyFraser D. Robinson, Louise H. Crockett, William H. Nailon, Robert W. Stewart. 1-2 [doi]
- An FPGA-based high-throughput stream join architectureCharalabos Kritikakis, Grigorios Chrysos, Apostolos Dollas, Dionisios N. Pnevmatikatos. 1-4 [doi]
- TeSHoP: A Temperature Sensing based Hotspot-Driven Placement technique for FPGAsWeina Lu, Yu Hu, Jing Ye, Xiaowei Li 0001. 1-4 [doi]
- Connect on the fly: Enhancing and prototyping of cycle-reconfigurable modulesHao Zhou, Xinyu Niu, Junqi Yuan, Lingli Wang, Wayne Luk. 1-8 [doi]
- Annotation-based finite-state transducers on reconfigurable devicesRaphael Polig, Kubilay Atasu, Christoph Hagleitner, Theresa Xu, Akihiro Nakayama. 1-9 [doi]
- A survey of AIS-20/31 compliant TRNG cores suitable for FPGA devicesOto Petura, Ugo Mureddu, Nathalie Bochard, Viktor Fischer, Lilian Bossuet. 1-10 [doi]
- DT-CGRA: Dual-track coarse-grained reconfigurable architecture for stream applicationsXitian Fan, Huimin Li, Wei Cao, Lingli Wang. 1-9 [doi]
- XNoC: A non-intrusive TDM circuit-switched Network-on-ChipTuan D. A. Nguyen, Akash Kumar 0001. 1-11 [doi]
- Bayesian inference implemented on FPGA with stochastic bitstreams for an autonomous robotHugo Fernandes, M. Awais Aslam, Jorge Lobo 0002, João Filipe Ferreira, Jorge Dias. 1-4 [doi]
- Exploring the use of shift register lookup tables for Keccak implementations on Xilinx FPGAsJori Winderickx, Joan Daemen, Nele Mentens. 1-4 [doi]
- A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structureDaisuke Suzuki, Takahiro Hanyu. 1-4 [doi]
- FMER: A hybrid configuration memory error recovery scheme for highly reliable FPGA SoCsDimitris Agiakatsikas, Ediz Çetin, Oliver Diessel. 1-4 [doi]
- JetStream: An open-source high-performance PCI Express 3 streaming library for FPGA-to-Host and FPGA-to-FPGA communicationMalte Vesper, Dirk Koch, Kizheppatt Vipin, Suhaib A. Fahmy. 1-9 [doi]
- ™Fellipe Montero, Guy Bois, Eric Jenn, Kevin Duplantier. 1 [doi]
- Liquid: Fast placement prototyping through steepest gradient descent movementElias Vansteenkiste, Seppe Lenders, Dirk Stroobandt. 1-4 [doi]
- Harnessing Programmable SoCs to develop cost-effective network quality monitoring devicesMario Ruiz, J. Ramos, Gustavo Sutter, Sergio López-Buedo, Jorge E. López de Vergara, C. Sisterna. 1-4 [doi]
- Resource efficient real-time processing of Contrast Limited Adaptive Histogram EqualizationBurak Unal, Ali Akoglu. 1-8 [doi]
- EURECA compilation: Automatic optimisation of cycle-reconfigurable circuitsXinyu Niu, Nicholas Ng, Tomofumi Yuki, Shaojun Wang, Nobuko Yoshida, Wayne Luk. 1-4 [doi]
- HeteroSim: A heterogeneous CPU-FPGA simulatorLiang Feng, Hao Liang, Sharad Sinha, Wei Zhang. 1 [doi]
- Effects of I/O routing through column interfaces in embedded FPGA fabricsChristophe Huriaux, Olivier Sentieys, Russell Tessier. 1-9 [doi]
- Time-borrowing platform in the Xilinx UltraScale+ family of FPGAs and MPSoCsIlya Ganusov, Benjamin Devlin. 1-9 [doi]
- Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformerW. Simon, A. C. Yuzuguler, A. Ibrahim, Federico Angiolini, M. Arditi, J. P. Thiran, Giovanni De Micheli. 1-2 [doi]
- Fast and robust hashing for database operatorsKaan Kara, Gustavo Alonso. 1-4 [doi]
- Improving the efficiency of PUF-based key generation in FPGAs using variation-aware placementShrikant Vyas, Naveen Kumar Dumpala, Russell Tessier, Daniel E. Holcomb. 1-4 [doi]
- GraVF: A vertex-centric distributed graph processing framework on FPGAsNina Engelhardt, Hayden Kwok-Hay So. 1-4 [doi]
- Optimizing interconnection complexity for realizing fixed permutation in data and signal processing algorithmsRen Chen, Viktor K. Prasanna. 1-9 [doi]
- Trojans modifying soft-processor instruction sequences embedded in FPGA bitstreamsIsmail San, Nicole Fern, Çetin Kaya Koç, Kwang-Ting Cheng. 1-4 [doi]
- High-speed programmable FPGA Configuration through JTAGAmmon Gruwell, Peter Zabriskie, Michael J. Wirthlin. 1-4 [doi]
- Hardware acceleration of feature detection and description algorithms on low-power embedded platformsOnur Ulusel, Christopher Picardo, Christopher B. Harris, Sherief Reda, R. Iris Bahar. 1-9 [doi]
- Fast hierarchical NPN classificationAna Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko. 1-4 [doi]
- PrefacePaolo Ienne, Walid A. Najjar, Jason Anderson, Philip Brisk, Walter Stechele. 1 [doi]
- AdapNoC: A fast and flexible FPGA-based NoC simulatorHadi Mardani Kamali, Shaahin Hessabi. 1-8 [doi]
- Stress-aware routing to mitigate aging effects in SRAM-based FPGAsBehnam Khaleghi, Behzad Omidi, Hussam Amrouch, Jörg Henkel, Hossein Asadi. 1-8 [doi]
- Body bias grain size exploration for a coarse grained reconfigurable acceleratorYusuke Matsushita, Hayate Okuhara, Koichiro Masuyama, Yu Fujita, Ryuta Kawano, Hideharu Amano. 1-4 [doi]
- An XDL alternative for interfacing RapidSmith and VivadoThomas Townsend, Brent E. Nelson, Michael J. Wirthlin. 1 [doi]
- A survey on reconfigurable accelerators for cloud computingChristoforos Kachris, Dimitrios Soudris. 1-10 [doi]
- Hoplite-DSP: Harnessing the Xilinx DSP48 multiplexers to efficiently support NoCs on FPGAsKumar H. B. Chethan, Nachiket Kapre. 1-10 [doi]
- Hardware-software codesign of RSA for optimal performance vs. flexibility trade-offMalik Umar Sharif, Rabia Shahid, Kris Gaj, Marcin Rogawski. 1-4 [doi]
- Approximate Frequent Itemset Mining for streaming data on FPGAYubin Li, Yuliang Sun, Guohao Dai, Qiang Xu, Yu Wang, Huazhong Yang. 1-4 [doi]
- The speed of diversity: Exploring complex FPGA routing topologies for the global metal layerOleg Petelin, Vaughn Betz. 1-10 [doi]
- Measure twice and cut once: Robust dynamic voltage scaling for FPGAsIbrahim Ahmed, Shuze Zhao, Olivier Trescases, Vaughn Betz. 1-11 [doi]
- SRI-SURF: A better SURF powered by scaled-RAM interpolator on FPGAXijie Jia, Kaiyuan Guo, Wenqiang Wang, Yu Wang 0002, Huazhong Yang. 1-8 [doi]
- Reconfigurable circuit for implementation of family of 4-phase latch protocolsJotham Vaddaboina Manoranjan, Kenneth S. Stevens. 1-4 [doi]
- Search-based synthesis of approximate circuits implemented into FPGAsZdenek Vasícek, Lukás Sekanina. 1-4 [doi]
- Transparent FPGA flowBaptiste Delporte, Anthony Convers, Roberto Rigamonti, Alberto Dassatti. 1 [doi]
- A hardware/software codesign framework for vision-based ADASLeandro Andrade Martinez, Eduardo Marques. 1-2 [doi]
- Modelling delay degradation due to NBTI in FPGA Look-up tablesMohammad Naouss, François Marc. 1-4 [doi]
- Towards a hardware-assisted information flow tracking ecosystem for ARM processorsMuhammad Abdul Wahab, Pascal Cotret, Mounir Nasr Allah, Guillaume Hiet, Vianney Lapotre, Guy Gogniat. 1-2 [doi]
- Optimizing hardware design for Human Action RecognitionXiaoyin Ma, Jose Rodriguez Borbon, Walid A. Najjar, Amit K. Roy Chowdhury. 1-11 [doi]
- Runtime reconfigurable beamforming architecture for real-time sound-source localizationBruno da Silva, Laurent Segers, An Braeken, Abdellah Touhafi. 1-4 [doi]
- Quantifying observability for in-system debug of high-level synthesis circuitsJeffrey Goeders, Steven J. E. Wilton. 1-11 [doi]
- Packet processing on FPGA SoC with DPDKJan Viktorin, Jan Korenek. 1-2 [doi]
- Scalable and modularized RTL compilation of Convolutional Neural Networks onto FPGAYufei Ma, Naveen Suda, Yu Cao, Jae-sun Seo, Sarma B. K. Vrudhula. 1-8 [doi]