Sidharth Maheshwari, Gourav Modi, Siddhartha, Nachiket Kapre. Vector FPGA acceleration of 1-D DWT computations using sparse matrix skeletons. In Paolo Ienne, Walid A. Najjar, Jason Anderson, Philip Brisk, Walter Stechele, editors, 26th International Conference on Field Programmable Logic and Applications, FPL 2016, Lausanne, Switzerland, August 29 - September 2, 2016. pages 1-4, IEEE, 2016. [doi]
Abstract is missing.