DPPC: Dynamic power partitioning and capping in chip multiprocessors

Kai Ma, Xiaorui Wang, Yefu Wang. DPPC: Dynamic power partitioning and capping in chip multiprocessors. In IEEE 29th International Conference on Computer Design, ICCD 2011, Amherst, MA, USA, October 9-12, 2011. pages 39-44, IEEE, 2011. [doi]

@inproceedings{MaWW11-0,
  title = {DPPC: Dynamic power partitioning and capping in chip multiprocessors},
  author = {Kai Ma and Xiaorui Wang and Yefu Wang},
  year = {2011},
  doi = {10.1109/ICCD.2011.6081373},
  url = {http://dx.doi.org/10.1109/ICCD.2011.6081373},
  researchr = {https://researchr.org/publication/MaWW11-0},
  cites = {0},
  citedby = {0},
  pages = {39-44},
  booktitle = {IEEE 29th International Conference on Computer Design, ICCD 2011, Amherst, MA, USA, October 9-12, 2011},
  publisher = {IEEE},
  isbn = {978-1-4577-1953-0},
}