Enrico Macii, Leticia Maria Veiras Bolzani, Andrea Calimera, Alberto Macii, Massimo Poncino. Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits. In Luca Fanucci, editor, 11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008. pages 298-303, IEEE, 2008. [doi]
@inproceedings{MaciiBCMP08,
title = {Integrating Clock Gating and Power Gating for Combined Dynamic and Leakage Power Optimization in Digital CMOS Circuits},
author = {Enrico Macii and Leticia Maria Veiras Bolzani and Andrea Calimera and Alberto Macii and Massimo Poncino},
year = {2008},
doi = {10.1109/DSD.2008.90},
url = {http://dx.doi.org/10.1109/DSD.2008.90},
tags = {optimization},
researchr = {https://researchr.org/publication/MaciiBCMP08},
cites = {0},
citedby = {0},
pages = {298-303},
booktitle = {11th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2008, Parma, Italy, September 3-5, 2008},
editor = {Luca Fanucci},
publisher = {IEEE},
isbn = {978-0-7695-3277-6},
}