Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks - researchr publication

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Enrico Macii, Massimo Poncino. Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks. In 5th Great Lakes Symposium on VLSI (GLS-VLSI 95), March 16-18, 1995, The State University of New York at Buffalo, USA. pages 60-65, IEEE Computer Society, 1995. [doi]

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