FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit Simulation

Yogesh Mahajan, Shashank Obla, Mini K. Namboothiripad, Mandar J. Datar, Niraj N. Sharma, Sachin B. Patkar. FPGA-Based Acceleration of LU decomposition for Analog and RF Circuit Simulation. In 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, VLSID 2020, Bangalore, India, January 4-8, 2020. pages 131-136, IEEE, 2020. [doi]

Authors

Yogesh Mahajan

This author has not been identified. Look up 'Yogesh Mahajan' in Google

Shashank Obla

This author has not been identified. Look up 'Shashank Obla' in Google

Mini K. Namboothiripad

This author has not been identified. Look up 'Mini K. Namboothiripad' in Google

Mandar J. Datar

This author has not been identified. Look up 'Mandar J. Datar' in Google

Niraj N. Sharma

This author has not been identified. Look up 'Niraj N. Sharma' in Google

Sachin B. Patkar

This author has not been identified. Look up 'Sachin B. Patkar' in Google