An efficient technique to select logic nodes for single event transient pulse-width reduction - researchr publication authors

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Nihaar N. Mahatme, Indranil Chatterjee, Akash Patki, Daniel B. Limbrick, Bharat L. Bhuva, Ronald D. Schrimpf, William H. Robinson. An efficient technique to select logic nodes for single event transient pulse-width reduction. Microelectronics Reliability, 53(1):114-117, 2013. [doi]

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