Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs

Ahmed Mahdi, Panagiotis Sakellariou, Nikos Kanistras, Ioannis Tsatsaragkos, Vassilis Paliouras. Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs. In 19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012. pages 89-92, IEEE, 2012. [doi]

@inproceedings{MahdiSKTP12,
  title = {Hardware design and verification techniques for Giga-bit Forward-Error Correction systems on FPGAs},
  author = {Ahmed Mahdi and Panagiotis Sakellariou and Nikos Kanistras and Ioannis Tsatsaragkos and Vassilis Paliouras},
  year = {2012},
  doi = {10.1109/ICECS.2012.6463792},
  url = {http://dx.doi.org/10.1109/ICECS.2012.6463792},
  researchr = {https://researchr.org/publication/MahdiSKTP12},
  cites = {0},
  citedby = {0},
  pages = {89-92},
  booktitle = {19th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2012, Seville, Spain, December 9-12, 2012},
  publisher = {IEEE},
  isbn = {978-1-4673-1259-2},
}