R. Maheshwari, S. S. S. P. Rao, E. G. Poonach. FPGA Implementation of Median Filter. In 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India. pages 523-524, IEEE Computer Society, 1997. [doi]
@inproceedings{MaheshwariRP97,
title = {FPGA Implementation of Median Filter},
author = {R. Maheshwari and S. S. S. P. Rao and E. G. Poonach},
year = {1997},
doi = {10.1109/ICVD.1997.568194},
url = {http://doi.ieeecomputersociety.org/10.1109/ICVD.1997.568194},
tags = {e-science},
researchr = {https://researchr.org/publication/MaheshwariRP97},
cites = {0},
citedby = {0},
pages = {523-524},
booktitle = {10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India},
publisher = {IEEE Computer Society},
}