Automated Design, Implementation, and Evaluation of Arbiter-based PUF on FPGA using Programmable Delay Lines

Mehrdad Majzoobi, Akshat Kharaya, Farinaz Koushanfar, Srinivas Devadas. Automated Design, Implementation, and Evaluation of Arbiter-based PUF on FPGA using Programmable Delay Lines. IACR Cryptology ePrint Archive, 2014:639, 2014. [doi]

@article{MajzoobiKKD14,
  title = {Automated Design, Implementation, and Evaluation of Arbiter-based PUF on FPGA using Programmable Delay Lines},
  author = {Mehrdad Majzoobi and Akshat Kharaya and Farinaz Koushanfar and Srinivas Devadas},
  year = {2014},
  url = {http://eprint.iacr.org/2014/639},
  researchr = {https://researchr.org/publication/MajzoobiKKD14},
  cites = {0},
  citedby = {0},
  journal = {IACR Cryptology ePrint Archive},
  volume = {2014},
  pages = {639},
}