Yatin A. Manerkar, Daniel Lustig, Margaret Martonosi, Michael Pellauer. RTLcheck: verifying the memory consistency of RTL designs. In Hillery C. Hunter, Jaime Moreno, Joel S. Emer, Daniel Sánchez 0003, editors, Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, October 14-18, 2017. pages 463-476, ACM, 2017. [doi]
@inproceedings{ManerkarLMP17,
title = {RTLcheck: verifying the memory consistency of RTL designs},
author = {Yatin A. Manerkar and Daniel Lustig and Margaret Martonosi and Michael Pellauer},
year = {2017},
doi = {10.1145/3123939.3124536},
url = {http://doi.acm.org/10.1145/3123939.3124536},
researchr = {https://researchr.org/publication/ManerkarLMP17},
cites = {0},
citedby = {0},
pages = {463-476},
booktitle = {Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 2017, Cambridge, MA, USA, October 14-18, 2017},
editor = {Hillery C. Hunter and Jaime Moreno and Joel S. Emer and Daniel Sánchez 0003},
publisher = {ACM},
isbn = {978-1-4503-4952-9},
}