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Analyzing cache performance bottlenecks of STM applications and addressing them with compiler s help

Sandya S. Mannarswamy, Ramaswamy Govindarajan. Analyzing cache performance bottlenecks of STM applications and addressing them with compiler s help. In Valentina Salapura, Michael Gschwind, Jens Knoop, editors, 19th International Conference on Parallel Architecture and Compilation Techniques (PACT 2010), Vienna, Austria, September 11-15, 2010. pages 547-548, ACM, 2010. [doi]

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Sandya S. Mannarswamy

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Ramaswamy Govindarajan

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