Refinement Maps for Efficient Verification of Processor Models

Panagiotis Manolios, Sudarshan K. Srinivasan. Refinement Maps for Efficient Verification of Processor Models. In 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany. pages 1304-1309, IEEE Computer Society, 2005. [doi]

Abstract

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