A data-aware write-assist 10T SRAM cell with bit-interleaving capability

Shivram Mansore, Radheshyam Gamad. A data-aware write-assist 10T SRAM cell with bit-interleaving capability. Turkish J. Electr. Eng. Comput. Sci., 26(5):2361-2373, 2018. [doi]

Abstract

Abstract is missing.