Zhiwei Mao, T. H. Szymansli. A 4Gb/s CMOS fully-differential analog dual delay-locked loop clock/data recovery circuit. In Proceedings of the 2003 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2003, Sharjah, United Arab Emirates, December 14-17, 2003. pages 559-562, IEEE, 2003. [doi]
Abstract is missing.