FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a Self-Clocked Approach - researchr publication

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José-Javier Martínez, F. Javier Toledo, F. Javier Garrigós, José Manuel Ferrández de Vicente. FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a Self-Clocked Approach. In Tero Rissa, Steven J. E. Wilton, Philip Heng Wai Leong, editors, Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), Tampere, Finland, August 24-26, 2005. pages 547-550, IEEE, 2005.

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