Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm

Nasser Masoumi, Mahmoud Ahmadian, Farshid Raissi, Massoud Masoumi, J. Ghasemi. Enhancing Performance and Saving Energy in CMOS DCVSL Gates by Using a New Transistor Sizing Algorithm. In Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 20-24 July 2004, Banff, Alberta, Canada. pages 283-288, IEEE Computer Society, 2005. [doi]

Abstract

Abstract is missing.