Hierarchical Test Analysis of VLSI Circuits for Random BIST - researchr publication

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G. Masseboeuf, J. Pulou, J. L. Rainard. Hierarchical Test Analysis of VLSI Circuits for Random BIST. In Klaus Echtle, Dieter K. Hammer, David Powell, editors, Dependable Computing - EDCC-1, First European Dependable Computing Conference, Berlin, Germany, October 4-6, 1994, Proceedings. Volume 852 of Lecture Notes in Computer Science, pages 271-288, Springer, 1994.

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