VLSI Architecture for High Performance 3GPP Interleaver/Deinterleaver for Turbo Codes

J. Magdalene Mathana, S. Badrinarayanan, Rani Hemamalini. VLSI Architecture for High Performance 3GPP Interleaver/Deinterleaver for Turbo Codes. Int. J. Comput. Commun. Control, 9(2):187-200, 2014. [doi]

Abstract

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