Bit-parallel systolic multiplier over GF ( 2 m ) for irreducible trinomials with ASIC and FPGA implementations

Sudha Ellison Mathe, Lakshmi Boppana. Bit-parallel systolic multiplier over GF ( 2 m ) for irreducible trinomials with ASIC and FPGA implementations. IET Circuits, Devices & Systems, 12(4):315-325, 2018. [doi]

Abstract

Abstract is missing.