A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter

Brett Mathis, James E. Stine. A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter. In 2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, FL, USA, July 15-17, 2019. pages 278-283, IEEE, 2019. [doi]

@inproceedings{MathisS19-0,
  title = {A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/Subtracter},
  author = {Brett Mathis and James E. Stine},
  year = {2019},
  doi = {10.1109/ISVLSI.2019.00058},
  url = {https://doi.org/10.1109/ISVLSI.2019.00058},
  researchr = {https://researchr.org/publication/MathisS19-0},
  cites = {0},
  citedby = {0},
  pages = {278-283},
  booktitle = {2019 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2019, Miami, FL, USA, July 15-17, 2019},
  publisher = {IEEE},
  isbn = {978-1-7281-3391-1},
}