Abstract is missing.
- Fast-ABC: A Fast Architecture for Bottleneck-Like Based Convolutional Neural NetworksXiaoru Xie, Fangxuan Sun, Jun Lin, Zhongfeng Wang. 1-6 [doi]
- On-Chip Instruction Generation for Cross-Layer CNN Accelerator on FPGAYiming Hu, Shuang Liang, Jincheng Yu, Yu Wang 0002, Huazhong Yang. 7-12 [doi]
- T-DLA: An Open-source Deep Learning Accelerator for Ternarized DNN Models on Embedded FPGAYao Chen, Kai Zhang, Cheng Gong, Cong Hao, Xiaofan Zhang, Tao Li, Deming Chen. 13-18 [doi]
- Optimization of Convolutional Neural Networks on Resource Constrained DevicesArish S, Sharad Sinha, Smitha K. G. 19-24 [doi]
- When Neural Architecture Search Meets Hardware Implementation: from Hardware Awareness to Co-DesignXinyi Zhang, Weiwen Jiang, Yiyu Shi, Jingtong Hu. 25-30 [doi]
- A Cost-Effective CNN Accelerator Design with Configurable PU on FPGAChi Fung Brian Fong, Jiandong Mu, Wei Zhang 0012. 31-36 [doi]
- Transient Effect Ring Oscillators Leak TooUgo Mureddu, Brice Colombier, Nathalie Bochard, Lilian Bossuet, Viktor Fischer. 37-42 [doi]
- Not All Feed-Forward MUX PUFs Generate Unique SignaturesAlex Ayling, Satya Venkata Sandeep Avvaru, Keshab K. Parhi. 43-48 [doi]
- SPN-DPUF: Substitution-Permutation Network Based Secure Circuit for Digital PUFJohan Marconot, David Hély, Florian Pebay-Peyroula. 49-54 [doi]
- Area Efficient Box Filter Acceleration by Parallelizing with Optimized Adder TreeXinzhe Liu, Fupeng Chen, Yajun Ha. 55-60 [doi]
- Towards Efficient Compact Network Training on Edge-DevicesFeng Xiong, Fengbin Tu, Shouyi Yin, Shaojun Wei. 61-67 [doi]
- Near-Memory and In-Storage FPGA Acceleration for Emerging Cognitive Computing WorkloadsAshutosh Dhar, Sitao Huang, Jinjun Xiong, Damir Jamsek, Bruno Mesnet, Jian Huang 0006, Nam Sung Kim, Wen-mei W. Hwu, Deming Chen. 68-75 [doi]
- Formal Verification of Integer Dividers: Division by a ConstantAtif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski. 76-81 [doi]
- PageCmp: Bandwidth Efficient Page Deduplication through In-memory Page ComparisonMehrnoosh Raoufi, Quan Deng, Youtao Zhang, Jun Yang. 82-87 [doi]
- An ESL Environment for Modeling Electrical Interconnect FaultsNooshin Nosrati, Katayoon Basharkhah, Rezgar Sadeghi, Zainalabedin Navabi. 88-93 [doi]
- Morphed Standard Cell Layouts for Pin Length ReductionCheng-Wei Tai, Rung-Bin Lin. 94-99 [doi]
- The Power of OrthogonalitySébastien Ollivier, Donald Kline Jr., Roxy A. Kawsher, Rami G. Melhem, Sanjukta Bhanja, Alex K. Jones. 100-102 [doi]
- In-memory AES Implementation for Emerging Non-Volatile Main MemoryMimi Xie, Yawen Wu, Zhenge Jia, Jingtong Hu. 103 [doi]
- Investigating Fairness in Disaggregated Non-Volatile MemoriesVamsee Reddy Kommareddy, Clayton Hughes, Simon D. Hammond, Amro Awad. 104-110 [doi]
- Pj-AxMTJ: Process-in-memory with Joint Magnetization Switching for Approximate Computing in Magnetic Tunnel JunctionHao Cai, Honglan Jiang, Menglin Han, Zhaohao Wang, You Wang, Jun Yang 0006, Jie Han 0001, Leibo Liu, Weisheng Zhao. 111-115 [doi]
- Dark-Silicon Inspired Energy Efficient Hierarchical TDM NoCSalma Hesham, Diana Goehringer, Mohamed A. Abd El ghany. 116-121 [doi]
- Traffic Driven Automated Synthesis of Network-on-Chip from Physically Aware Behavioral SpecificationAnup Gangwar, Zheng Xu, Nitin Kumar Agarwal, Ravishankar Sreedharan, Ambica Prasad. 122-127 [doi]
- Automated Communication and Floorplan-Aware Hardware/Software Co-Design for SoCJong Bin Lim, Deming Chen. 128-133 [doi]
- Computationally Efficient Learning of Quality Controlled Word Embeddings for Natural Language ProcessingMohammed Alawad, Georgia D. Tourassi. 134-139 [doi]
- Formal Hardware Verification of InfoSec PrimitivesMohamed Asan Basiri M, Sandeep K. Shukla. 140-145 [doi]
- SRAM On-Chip Monitoring Methodology for Energy Efficient Memory Operation at Near Threshold VoltageTaehwan Kim 0007, Kwangok Jeong, Taewhan Kim, Kyu-Myung Choi. 146-151 [doi]
- Energy and Error Reduction using Variable Bit-width Optimization on Dynamic Fixed Point FormatMingze Gao, Qian Wang, Gang Qu. 152-157 [doi]
- Machine Learning-Based Processor Adaptability Targeting Energy, Performance, and ReliabilityAnderson Luiz Sartor, Pedro Henrique Exenberger Becker, Stephan Wong, Radu Marculescu, Antonio Carlos Schneider Beck. 158-163 [doi]
- Energy-Efficient Embedded Inference of SVMs on FPGAOsman Elgawi, A. M. Mutawa, Afaq Ahmad 0001. 164-168 [doi]
- A Reconfigurable Layered-Based Bio-Inspired Smart Image SensorPankaj Bhowmik, Md Jubaer Hossain Pantho, Sujan Saha, Christophe Bobda. 169-174 [doi]
- An Asynchronous Analog to Digital Converter for Video Camera ApplicationsSunil R., R. K. Siddharth, Nithin Y. B. Kumar, M. H. Vasantha. 175-180 [doi]
- Design of Switched-Current Based Low-Power PIM Vision System for IoT ApplicationsZheyu Liu, Zichen Fan, Qi Wei 0001, Xing Wu, Fei Qiao, Ping Jin, Xinjun Liu, Chengliang Liu, Huazhong Yang. 181-186 [doi]
- IDE Development, Logic Synthesis and Buffer/Splitter Insertion Framework for Adiabatic Quantum-Flux-Parametron Superconducting CircuitsRuizhe Cai, Xiaolong Ma, Olivia Chen, Ao Ren, Ning Liu, Nobuyuki Yoshikawa, Yanzhi Wang. 187-192 [doi]
- A Framework for the Analysis of Throughput-Constraints of SNNs on Neuromorphic HardwareAdarsha Balaji, Anup Das 0001. 193-196 [doi]
- Accelerating Deep Neural Networks in Processing-in-Memory Platforms: Analog or Digital Approach?Shaahin Angizi, Zhezhi He, Dayane Reis, Xiaobo Sharon Hu, Wilman Tsai, Shy Jay Lin, Deliang Fan. 197-202 [doi]
- Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks AccelerationYinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang, Youguang Zhang, Weisheng Zhao. 203-206 [doi]
- An Area Effective Programmable Front-end Amplifier for Neural Signal AcquisitionGopabandhu Hota, Hardik Agrawal, Mrigank Sharad. 207-211 [doi]
- Minimization of Flare in EUVL by Simultaneous Wire Segment Perturbation and DummificationSudipta Paul 0001, Pritha Banerjee, Susmita Sur-Kolay. 212-217 [doi]
- Exploration and Exploitation of Dual Timing Margins for Improving Power Efficiency of Variable-Latency DesignsNing-Chi Huang, Yu-Guang Chen, Kai-Chiang Wu. 218-223 [doi]
- Improving Logic Optimization in Sequential Circuits using Majority-inverter GraphsWalter Lau Neto, Xifan Tang, Max Austin, Luca G. Amarù, Pierre-Emmanuel Gaillardon. 224-229 [doi]
- Design of a CMOS Broadband Transimpedance Amplifier with Floating Active InductorXiangyu Chen, Yasuhiro Takahashi. 230-234 [doi]
- Distributed Pulse Rotary Traveling Wave VCO: Architecture and DesignPrashansa Mukim, Aditya Dalakoti, David McCarthy, Brandon Pon, Carrie Segal, Merritt Miller, James F. Buckwalter, Forrest Brewer. 235-240 [doi]
- Test Your Test Programs Pre-Silicon: A Virtual Test Methodology for Industrial Design FlowsSebastian Pointner, Oliver Frank, Christoph Hazott, Robert Wille. 241-246 [doi]
- Design of a Safe Convolutional Neural Network AcceleratorZheng Xu, Jacob Abraham. 247-252 [doi]
- Test Point Insertion Using Artificial Neural NetworksYang Sun, Spencer K. Millican. 253-258 [doi]
- Evaluation of Compilers Effects on OpenMP Soft Error ResiliencyJonas Gava, Vitor Bandiera, Ricardo Reis, Luciano Ost. 259-264 [doi]
- A One-Cycle FIFO Buffer for Memory Management Units in Manycore SystemsAnn Gordon-Ross, Saleh Abdel-Hafeez, Mohamad Hammam Alsafrjalani. 265-270 [doi]
- Impact of Autocorrelation on Stochastic Circuit AccuracyTimothy Baker, John Hayes. 271-277 [doi]
- A Novel Single/Double Precision Normalized IEEE 754 Floating-Point Adder/SubtracterBrett Mathis, James E. Stine. 278-283 [doi]
- Tackling the Drawbacks of a Lagrangian Relaxation Based Discrete Gate Sizing AlgorithmHenrique Placido, Ricardo Reis. 284-289 [doi]
- A Dual-Band CMOS Low-Noise Amplifier using Memristor-Based Tunable InductorsNicolás Wainstein, Tamir Tsabari, Yarden Goldin, Eilam Yalon, Shahar Kvatinsky. 290-295 [doi]
- Micro-electrode-dot Array Based Biochips : Advantages of Using Different Shaped CMAsPampa Howladar, Pranab Roy, Hafizur Rahaman. 296-301 [doi]
- An Improved Automatic Hardware Trojan Generation PlatformShichao Yu, Weiqiang Liu, Máire O'Neill. 302-307 [doi]
- TrustFlow: A Trusted Memory Support for Data Flow IntegrityCyril Bresch, David Hély, Stéphanie Chollet, Ioannis Parissis. 308-313 [doi]
- Enabling Microarchitectural Randomization in Serialized AES Implementations to Mitigate Side Channel SusceptibilitySiva Nishok Dhanuskodi, Daniel Holcomb. 314-319 [doi]
- Securing a Wireless Network-on-Chip Against Jamming Based Denial-of-Service AttacksAbhishek Vashist, Andrew Keats, Sai Manoj Pudukotai Dinakarrao, Amlan Ganguly. 320-325 [doi]
- FAST: A Frequency-Aware Skewed Merkle Tree for FPGA-Secured Embedded SystemsYu Zou, Mingjie Lin. 326-331 [doi]
- Defense-Net: Defend Against a Wide Range of Adversarial Attacks through Adversarial DetectorAdnan Siraj Rakin, Deliang Fan. 332-337 [doi]
- Deep State Encryption for Sequential Logic CircuitsYasaswy Kasarabada, Sudheer Ram Thulasi Raman, Ranga Vemuri. 338-343 [doi]
- A Multi-phase Time-to-Digital Converter Differential Vernier Ring OscillatoAmina Annagrebah, E. Bechetoille, I. B. Laktineh, H. Chanal, P. Russo, H. Mathez. 344-347 [doi]
- ASSET: Architectures for Smart Security of Non-Volatile MemoriesShivam Swami, Kartik Mohanram. 348-353 [doi]
- IRC Cross-Layer Design Exploration of Intermittent Robust Computation Units for IoTsArman Roohi, Ronald F. DeMara. 354-359 [doi]
- Design of Quantum Circuits for Cryptanalysis and Image Processing ApplicationsEdgard Muñoz-Coreas, Himanshu Thapliyal. 360-365 [doi]
- Effect of Loop Positions on Reliability and Attack Resistance of Feed-Forward PUFsSatya Venkata Sandeep Avvaru, Keshab K. Parhi. 366-371 [doi]
- A Case Study On Approximate FPGA Design With an Open-Source Image Processing PlatformYunxiang Zhang, Xiaokun Yang, Lei Wu, Jean Andrian. 372-377 [doi]
- Real-Time Automatic Music Transcription (AMT) with Zync FPGAKevin Vaca, Archit Gajjar, Xiaokun Yang. 378-384 [doi]
- An Approximate Multiply-Accumulate Unit with Low Power and Reduced AreaTongxin Yang, Toshinori Sato, Tomoaki Ukezono. 385-390 [doi]
- A Low-Power Recurrence-Based Radix 4 Divider Using Signed-Digit AdditionMatthew Gaalswyk, James E. Stine. 391-396 [doi]
- Towards Data-Driven Approximate Circuit DesignLing Qiu, Ziji Zhang, Jon Calhoun, Yingjie Lao. 397-402 [doi]
- MRAM-Based Stochastic Oscillators for Adaptive Non-Uniform Sampling of Sparse Signals in IoT ApplicationsSoheil Salehi, Alireza Zaeemzadeh, Adrian Tatulian, Nazanin Rahnavard, Ronald F. DeMara. 403-408 [doi]
- Evaluation of Power Analysis Attacks on Cryptographic Circuit Using Adiabatic LogicHiroki Koyasu, Yasuhiro Takahashi. 409-413 [doi]
- Approximate Energy Recovery 4-2 Compressor for Low-Power Sub-GHz IoT ApplicationsHimanshu Thapliyal, Zachary Kahleifeh. 414-418 [doi]
- Routing Performance Optimization for Homogeneous Droplets on MEDA-based Digital Microfluidic BiochipsSarit Chakraborty, Susanta Chakraborty. 419-424 [doi]
- Time-Constrained Sample Preparation Algorithm for Reactant Minimization on Digital Microfluidic BiochipsLing-Yen Song, Yu-Ying Li, Yung-Chun Lei, Juinn-Dar Huang. 425-430 [doi]
- Logic Synthesis for Hybrid CMOS-ReRAM Sequential CircuitsSaman Fröhlich, Saeideh Shirinzadeh, Rolf Drechsler. 431-436 [doi]
- Ferroelectric FET Based TCAM Designs for Energy Efficient ComputingXunzhao Yin, Dayane Reis, Michael T. Niemier, Xiaobo Sharon Hu. 437-442 [doi]
- Post-Layout Simulation of Quasi-Adiabatic Logic Based Physical Unclonable FunctionYasuhiro Takahashi, Hiroki Koyasu, S. Dinesh Kumar, Himanshu Thapliyal. 443-446 [doi]
- A 1.8mW Perception Chip with Near-Sensor Processing Scheme for Low-Power AIoT ApplicationsZheyu Liu, Erxiang Ren, Li Luo, Qi Wei 0001, Xing Wu, Xueqing Li, Fei Qiao, Xin-Jun Liu, Huazhong Yang. 447-452 [doi]
- Linear Optimization for Memristive Device in Neuromorphic HardwareJingyan Fu, Zhiheng Liao, Na Gong, Jinhui Wang. 453-458 [doi]
- Neuromorphic Image Sensor Design with Region-Aware ProcessingMd Jubaer Hossain Pantho, Pankaj Bhowmik, Christophe Bobda. 459-464 [doi]
- CSrram: Area-Efficient Low-Power Ex-Situ Training Framework for Memristive Neuromorphic Circuits Based on Clustered SparsityArash Fayyazi, Souvik Kundu, Shahin Nazarian, Peter A. Beerel, Massoud Pedram. 465-470 [doi]
- Security in Many-Core SoCs Leveraged by Opaque Secure ZonesLuciano L. Caimi, Fernando Gehm Moraes. 471-476 [doi]
- CAESAR-MPSoC: Dynamic and Efficient MPSoC Security ZonesSiavoosh Payandeh Azad, Gert Jervan, Michael Tempelmeier, Johanna Sepúlveda. 477-482 [doi]
- Modeling Hardware Trojans in 3D ICsZhiming Zhang, Qiaoyan Yu. 483-488 [doi]
- A Low-Complexity RS Decoder for Triple-Error-Correcting RS CodesZengchao Yan, Jun Lin, Zhongfeng Wang. 489-494 [doi]
- Optimization of Comparator Selection Algorithm for TIQ Flash ADC Using Dynamic Programming ApproachAli Ozdemir, Mshabab Alrizah, Kyusun Choi. 495-500 [doi]
- TSV-IaS: Analytic Analysis and Low-Cost Non-Preemptive on-Line Detection and Correction Method for TSV DefectsKhanh N. Dang, Akram Ben Ahmed, Abderazek Ben Abdallah, Xuan-Tu Tran. 501-506 [doi]
- Energy-efficient Analog Processing Architecture for Direction of Arrival with Microphone ArrayChanglu Liu, Tianxiang Lan, Qin Li, Kaige Jia, Yidian Fan, Xing Wu, Fei Qiao, Wei Qi, Xin-Jun Liu, Huazhong Yang. 507-512 [doi]
- iMACE: In-Memory Acceleration of Classic McEliece EncoderKarthikeyan Nagarajan, Sina Sayyah Ensan, Swagata Mandal, Swaroop Ghosh, Anupam Chattopadhyay. 513-518 [doi]
- Accelerating Compact Convolutional Neural Networks with Multi-threaded Data StreamingWeiguang Chen, Zheng Wang, Shanliao Li, Zhibin Yu, Huijuan Li. 519-522 [doi]
- Design of a Hierarchical Clos-Benes Optical Network-on-Chip ArchitectureRenjie Yao, Yaoyao Ye, Weichen Liu. 523-528 [doi]
- Machine Learning-based Prediction for Phase-Based Dynamic Architectural SpecializationRuben Vazquez, Islam Badreldin, Mohamad Hammam Alsafrjalani, Ann Gordon-Ross. 529-534 [doi]
- Hybrid Memristor-CMOS Obfuscation Against Untrusted FoundriesAmin Rezaei, Jie Gu, Hi Zhou. 535-540 [doi]
- Memory Locking: An Automated Approach to Processor Design ObfuscationMichael Zuzak, Ankur Srivastava. 541-546 [doi]
- Hardware-Software Co-Design Based Obfuscation of Hardware AcceleratorsAbhishek Chakraborty 0001, Ankur Srivastava. 547-552 [doi]
- Deep Learning for Edge Computing: Current Trends, Cross-Layer Optimizations, and Open Research ChallengesAlberto Marchisio, Muhammad Abdullah Hanif, Faiq Khalid, George Plastiras, Christos Kyrkou, Theocharis Theocharides, Muhammad Shafique 0001. 553-559 [doi]
- Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing MapsDimitrios Stathis 0003, Yu Yang, Saurabh Tewari, Ahmed Hemani, Kolin Paul, Manfred Grabherr, Rafi Ahmad. 560-567 [doi]
- Towards Efficient On-Board Deployment of DNNs on Intelligent Autonomous SystemsAlexandros Kouris, Stylianos I. Venieris, Christos-Savvas Bouganis. 568-573 [doi]
- PVTMC: An All-Digital Sub-Picosecond Timing Measurement Circuit Based on Process VariationsShuo Li, Xiaolin Xu, Wayne Burleson. 574-579 [doi]
- Hardware Implementation of Improved Fast-SSC-Flip Decoder for Polar CodesJing Zeng, Yangcan Zhou, Jun Lin, Zhongfeng Wang. 580-585 [doi]
- A Comparison-free Hardware Sorting EngineSurajeet Ghosh, Shaon Dasgupta, Sanchita Saha Ray. 586-591 [doi]
- Adaptive Transceiver for Wireless NoC to Enhance Multicast/Unicast Communication ScenariosJoel Ortiz Sosa, Olivier Sentieys, Christian Roland. 592-597 [doi]
- Countering Botnet of Things using Blockchain-Based Authenticity FrameworkPinchen Cui, Ujjwal Guin. 598-603 [doi]
- Aging Analysis of Low Dropout Regulator for Universal Recycled IC DetectionSreeja Chowdhury, Hao-Ting Shen, Beomsoo Park, Nima Maghari, Domenic Forte. 604-609 [doi]
- Persistently-Secure Processors: Challenges and Opportunities for Securing Non-Volatile MemoriesAmro Awad, Suboh Suboh, Mao Ye, Kazi Abu Zubair, Mazen Al-Wadi. 610-614 [doi]
- Focus on What is Needed: Area and Power Efficient FPGAs Using Turn-Restricted Switch BoxesFatemeh Serajeh-hassani, Mohammad Sadrosadati, Sebastian Pointner, Robert Wille, Hamid Sarbazi-Azad. 615-620 [doi]
- Using Harmonized Parabolic Synthesis to Implement a Single-Precision Floating-Point Square Root UnitSüleyman Savas, Yassin Atwa, Tomas Nordström, Zain-ul-Abdin. 621-626 [doi]
- Self Timed SRAM Array with Enhanced low Voltage Read and Write CapabilityPrasad Vernekar, Nithin Kumar Yernad Balachandra, Vasantha Moodabettu Harishchandra. 627-631 [doi]
- Towards Hardware-Assisted Security for IoT SystemsYier Jin. 632-637 [doi]
- Blockchain Based Distributed Key Provisioning and Secure Communication over CAN FDBryson Shannon, Spandana Etikala, Yutian Gui, Ali Shuja Siddiqui, Fareena Saqib. 638-644 [doi]
- A Hyper-Parameter Based Margin Calculation Algorithm for Single Flux Quantum Logic CellsSoheil Nazar Shahsavani, Massoud Pedram. 645-650 [doi]
- Ignore Clocking Constraints: An Alternative Physical Design Methodology for Field-Coupled NanotechnologiesRobert Wille, Marcel Walter, Frank Sill Torres, Daniel Große, Rolf Drechsler. 651-656 [doi]
- Mitigating Reverse Engineering Attacks on Deep Neural NetworksYuntao Liu 0001, Dana Dachman-Soled, Ankur Srivastava. 657-662 [doi]
- Hardware Watermarking Using Polymorphic Inverter Designs Based On Reconfigurable NanotechnologiesShubham Rai, Ansh Rupani, Pallab Nath, Akash Kumar 0001. 663-669 [doi]
- Machine Learning Based IoT Edge Node Security Attack and CountermeasuresVishalini R. Laguduva, Sheikh Ariful Islam, Sathyanarayanan N. Aakur, Srinivas Katkoori, Robert Karam. 670-675 [doi]