Brett Mathis, James E. Stine. A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter. In 30th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2019, New York, NY, USA, July 15-17, 2019. pages 227-234, IEEE, 2019. [doi]
@inproceedings{MathisS19,
title = {A Well-Equipped Implementation: Normal/Denormalized Half/Single/Double Precision IEEE 754 Floating-Point Adder/Subtracter},
author = {Brett Mathis and James E. Stine},
year = {2019},
doi = {10.1109/ASAP.2019.00011},
url = {https://doi.org/10.1109/ASAP.2019.00011},
researchr = {https://researchr.org/publication/MathisS19},
cites = {0},
citedby = {0},
pages = {227-234},
booktitle = {30th IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2019, New York, NY, USA, July 15-17, 2019},
publisher = {IEEE},
isbn = {978-1-7281-1601-3},
}