Go Matsukawa, Yohei Nakata, Yuta Kimi, Yasuo Sugure, Masafumi Shimozawa, Shigeru Oho, Hiroshi Kawaguchi, Masahiko Yoshimoto, Masahiko Yoshimoto. A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM. In Walter Stechele, Thomas Wild, editors, ARCS 2014 - 27th International Conference on Architecture of Computing Systems, Workshop Proceedings, February 25-28, 2014, Luebeck, Germany, University of Luebeck, Institute of Computer Engineering. pages 1-5, VDE Verlag / IEEE Xplore, 2014. [doi]
@inproceedings{MatsukawaNKSSOKYY14,
title = {A Low-Latency DMR Architecture with Efficient Recovering Scheme Exploiting Simultaneously Copiable SRAM},
author = {Go Matsukawa and Yohei Nakata and Yuta Kimi and Yasuo Sugure and Masafumi Shimozawa and Shigeru Oho and Hiroshi Kawaguchi and Masahiko Yoshimoto and Masahiko Yoshimoto},
year = {2014},
url = {http://ieeexplore.ieee.org/xpl/articleDetails.jsp?arnumber=6775097},
researchr = {https://researchr.org/publication/MatsukawaNKSSOKYY14},
cites = {0},
citedby = {0},
pages = {1-5},
booktitle = {ARCS 2014 - 27th International Conference on Architecture of Computing Systems, Workshop Proceedings, February 25-28, 2014, Luebeck, Germany, University of Luebeck, Institute of Computer Engineering},
editor = {Walter Stechele and Thomas Wild},
publisher = {VDE Verlag / IEEE Xplore},
isbn = {978-3-8007-3579-2},
}