Shota Matsuno, Masashi Tawada, Nozomu Togawa. Reducing Writing Energy Consumption for Non-Volatile Registers Utilizing Frequent Patterns of Sequential Bits on RISC-V Architecture. In IEEE International Conference on Consumer Electronics, ICCE 2021, Las Vegas, NV, USA, January 10-12, 2021. pages 1-6, IEEE, 2021. [doi]
Abstract is missing.