Tatsuji Matsuura, Takashi Nara, Tatsuya Komatsu, Eiki Imaizumi, Toshihiro Matsutsuru, Ryutaro Horita, Haruto Katsu, Shintaro Suzumura, Kazuo Sato. A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter. J. Solid-State Circuits, 33(11):1840-1850, 1998. [doi]
@article{MatsuuraNKIMHKS98,
title = {A 240-Mbps, 1-W CMOS EPRML read-channel LSI chip using an interleaved subranging pipeline A/D converter},
author = {Tatsuji Matsuura and Takashi Nara and Tatsuya Komatsu and Eiki Imaizumi and Toshihiro Matsutsuru and Ryutaro Horita and Haruto Katsu and Shintaro Suzumura and Kazuo Sato},
year = {1998},
doi = {10.1109/4.726586},
url = {https://doi.org/10.1109/4.726586},
researchr = {https://researchr.org/publication/MatsuuraNKIMHKS98},
cites = {0},
citedby = {0},
journal = {J. Solid-State Circuits},
volume = {33},
number = {11},
pages = {1840-1850},
}