Reduced Hardware NOrec: A Safe and Scalable Hybrid Transactional Memory

Alexander Matveev, Nir Shavit. Reduced Hardware NOrec: A Safe and Scalable Hybrid Transactional Memory. In Özcan Özturk, Kemal Ebcioglu, Sandhya Dwarkadas, editors, Proceedings of the Twentieth International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS '15, Istanbul, Turkey, March 14-18, 2015. pages 59-71, ACM, 2015. [doi]

Abstract

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