Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs

A. Maxim, B. Scott, E. Schneider, M. Hagge, S. Chacko, Dan Stiurca. Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs. In International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia. pages 766-769, IEEE, 2001. [doi]

Abstract

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