A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages

Yavar Safaei Mehrabani, Zahra Zareei, Ahmad Khademzadeh. A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages. IJHPSA, 4(4):196-203, 2013. [doi]

@article{MehrabaniZK13,
  title = {A high-speed and high-performance full adder cell based on 32-nm CNFET technology for low voltages},
  author = {Yavar Safaei Mehrabani and Zahra Zareei and Ahmad Khademzadeh},
  year = {2013},
  doi = {10.1504/IJHPSA.2013.058975},
  url = {http://dx.doi.org/10.1504/IJHPSA.2013.058975},
  researchr = {https://researchr.org/publication/MehrabaniZK13},
  cites = {0},
  citedby = {0},
  journal = {IJHPSA},
  volume = {4},
  number = {4},
  pages = {196-203},
}