Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor

Vazgen Melikyan, Eduard Babayan, Anush Melikyan, Davit Babayan, Poghos Petrosyan, Edvard Mkrtchyan. Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor. In 2015 IEEE East-West Design & Test Symposium, EWDTS 2015, Batumi, Georgia, September 26-29, 2015. pages 1-4, IEEE Computer Society, 2015. [doi]

@inproceedings{MelikyanBMBPM15,
  title = {Clock gating and multi-VTH low power design methods based on 32/28 nm ORCA processor},
  author = {Vazgen Melikyan and Eduard Babayan and Anush Melikyan and Davit Babayan and Poghos Petrosyan and Edvard Mkrtchyan},
  year = {2015},
  doi = {10.1109/EWDTS.2015.7493159},
  url = {http://doi.ieeecomputersociety.org/10.1109/EWDTS.2015.7493159},
  researchr = {https://researchr.org/publication/MelikyanBMBPM15},
  cites = {0},
  citedby = {0},
  pages = {1-4},
  booktitle = {2015 IEEE East-West Design & Test Symposium, EWDTS 2015, Batumi, Georgia, September 26-29, 2015},
  publisher = {IEEE Computer Society},
  isbn = {978-1-4673-7776-8},
}