A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation - researchr publication authors

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Swapnil Mhaske, David Uliana, Hojin Kee, Tai Ly, Ahsan Aziz, Predrag Spasojevic. A 2.48Gb/s FPGA-based QC-LDPC decoder: An algorithmic compiler implementation. In 2015 36th IEEE Sarnoff Symposium, Newark, NJ, USA, September 20-22, 2015. pages 88-93, IEEE, 2015. [doi]

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