Mapping for better than worst-case delays in LUT-based FPGA designs

Kirill Minkovich, Jason Cong. Mapping for better than worst-case delays in LUT-based FPGA designs. In Mike Hutton, Paul Chow, editors, Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008. pages 56-64, ACM, 2008. [doi]

@inproceedings{MinkovichC08,
  title = {Mapping for better than worst-case delays in LUT-based FPGA designs},
  author = {Kirill Minkovich and Jason Cong},
  year = {2008},
  doi = {10.1145/1344671.1344681},
  url = {http://doi.acm.org/10.1145/1344671.1344681},
  tags = {rule-based},
  researchr = {https://researchr.org/publication/MinkovichC08},
  cites = {0},
  citedby = {0},
  pages = {56-64},
  booktitle = {Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008},
  editor = {Mike Hutton and Paul Chow},
  publisher = {ACM},
  isbn = {978-1-59593-934-0},
}