A low voltage CMOS analog multiplier with high linearity - researchr publication authors

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Amir H. Miremadi, Ahmad Ayatollahi, Adib Abrishamifar, Alireza Siadatan. A low voltage CMOS analog multiplier with high linearity. In 19th European Conference on Circuit Theory and Design, ECCTD 2009, Antalya, Turkey, August 23-27, 2009. pages 257-262, IEEE, 2009. [doi]

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