A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology - researchr publication authors

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Jitendra Kumar Mishra, Harshit Srivastava, Prasanna Kumar Misra, Manish Goswami. A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology. In IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018. pages 1-5, IEEE, 2018. [doi]

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