A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology

Jitendra Kumar Mishra, Harshit Srivastava, Prasanna Kumar Misra, Manish Goswami. A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology. In IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018. pages 1-5, IEEE, 2018. [doi]

@inproceedings{MishraSMG18,
  title = {A 40nm Low Power High Stable SRAM Cell Using Separate Read Port and Sleep Transistor Methodology},
  author = {Jitendra Kumar Mishra and Harshit Srivastava and Prasanna Kumar Misra and Manish Goswami},
  year = {2018},
  doi = {10.1109/iSES.2018.00011},
  url = {https://doi.org/10.1109/iSES.2018.00011},
  researchr = {https://researchr.org/publication/MishraSMG18},
  cites = {0},
  citedby = {0},
  pages = {1-5},
  booktitle = {IEEE International Symposium on Smart Electronic Systems, iSES 2018 (Formerly iNiS), Hyderabad, India, December 17-19, 2018},
  publisher = {IEEE},
  isbn = {978-1-5386-9172-4},
}