A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU - researchr publication

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Seiji Miura, Kazushige Ayukawa, Takao Watanabe. A dynamic-SDRAM-mode-control scheme for low-power systems with a 32-bit RISC CPU. In Enrico Macii, Vivek De, Mary Jane Irwin, editors, Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001, Huntington Beach, California, USA, 2001. pages 358-363, ACM, 2001. [doi]

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