Hiroyuki Mizuno, Koichiro Ishibashi. A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio. IEEE Trans. VLSI Syst., 7(1):139-144, 1999. [doi]
@article{MizunoI99,
title = {A separated bit-line unified cache: Conciliating small on-chip cache die-area and low miss ratio},
author = {Hiroyuki Mizuno and Koichiro Ishibashi},
year = {1999},
doi = {10.1109/92.748213},
url = {http://doi.ieeecomputersociety.org/10.1109/92.748213},
tags = {caching},
researchr = {https://researchr.org/publication/MizunoI99},
cites = {0},
citedby = {0},
journal = {IEEE Trans. VLSI Syst.},
volume = {7},
number = {1},
pages = {139-144},
}