A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators - researchr publication authors

researchr

You are not signed in
Sign in
Sign up

Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure. A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators. J. Solid-State Circuits, 31(11):1618-1624, 1996. [doi]

This author has not been identified. Look up 'Hiroyuki Mizuno' in GoogleThis author has not been identified. Look up 'Nozomu Matsuzaki' in GoogleThis author has not been identified. Look up 'Kenichi Osada' in GoogleThis author has not been identified. Look up 'Toshinobu Shinbo' in GoogleThis author has not been identified. Look up 'Nagatoshi Ohki' in GoogleThis author has not been identified. Look up 'Hiroshi Ishida' in GoogleThis author has not been identified. Look up 'Koichiro Ishibashi' in GoogleThis author has not been identified. Look up 'Tokuo Kure' in Google

runs on WebDSL