An Efficient Design of Single Event Transients Tolerance for Logic Circuits - researchr publication authors

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Yantu Mo, Suge Yue. An Efficient Design of Single Event Transients Tolerance for Logic Circuits. In 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2008, Hong Kong, January 23-25, 2008. pages 125-128, IEEE Computer Society, 2008. [doi]

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