Sangman Moh. VLSI-Oriented Architecture for Two's Complement Serial-Parallel Multiplication without Speed Penalty. In Marina L. Gavrilova, Osvaldo Gervasi, editors, Selected Papers of the Fifth International Conference on, Computational Science and its Applications, ICCSA 2007, Kuala Lumpur, Malaysia, August 26-29, 2007. pages 9-13, IEEE Computer Society, 2007. [doi]
@inproceedings{Moh07-0,
title = {VLSI-Oriented Architecture for Two's Complement Serial-Parallel Multiplication without Speed Penalty},
author = {Sangman Moh},
year = {2007},
doi = {10.1109/ICCSA.2007.56},
url = {http://doi.ieeecomputersociety.org/10.1109/ICCSA.2007.56},
researchr = {https://researchr.org/publication/Moh07-0},
cites = {0},
citedby = {0},
pages = {9-13},
booktitle = {Selected Papers of the Fifth International Conference on, Computational Science and its Applications, ICCSA 2007, Kuala Lumpur, Malaysia, August 26-29, 2007},
editor = {Marina L. Gavrilova and Osvaldo Gervasi},
publisher = {IEEE Computer Society},
isbn = {0-7695-2945-3},
}