Automatic test pattern generation for virtual hardware model using constrained symbolic execution - researchr publication authors

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Nahla Mohamed, Mona Safar, Ayman M. Wahba, Ashraf Salem. Automatic test pattern generation for virtual hardware model using constrained symbolic execution. In 10th International Design & Test Symposium, IDT 2015, Dead Sea, Amman, Jordan, December 14-16, 2015. pages 149-150, IEEE, 2015. [doi]

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