A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL

Kartik Mohanram, C. V. Krishna, Nur A. Touba. A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL. In ISCAS (1). pages 577-580, 2002. [doi]

@inproceedings{MohanramKT02,
  title = {A methodology for automated insertion of concurrent error detection hardware in synthesizable Verilog RTL},
  author = {Kartik Mohanram and C. V. Krishna and Nur A. Touba},
  year = {2002},
  doi = {10.1109/ISCAS.2002.1009906},
  url = {http://doi.ieeecomputersociety.org/10.1109/ISCAS.2002.1009906},
  tags = {C++},
  researchr = {https://researchr.org/publication/MohanramKT02},
  cites = {0},
  citedby = {0},
  pages = {577-580},
  booktitle = {ISCAS (1)},
}