Saraju P. Mohanty, Elias Kougianos, Nagarajan Ranganathan. VLSI architecture and chip for combined invisible robust and fragile watermarking. IET Computers & Digital Techniques, 1(5):600-611, 2007. [doi]
@article{MohantyKR07, title = {VLSI architecture and chip for combined invisible robust and fragile watermarking}, author = {Saraju P. Mohanty and Elias Kougianos and Nagarajan Ranganathan}, year = {2007}, doi = {10.1049/iet-cdt:20070057}, url = {http://dx.doi.org/10.1049/iet-cdt:20070057}, tags = {watermarking, architecture}, researchr = {https://researchr.org/publication/MohantyKR07}, cites = {0}, citedby = {0}, journal = {IET Computers & Digital Techniques}, volume = {1}, number = {5}, pages = {600-611}, }