A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC - researchr publication authors

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Satyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra, Sanjeev Mehta, Arup Roy Chowdhury, Nisha Pandya. A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADC. In 32nd International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems, VLSID 2019, Delhi, India, January 5-9, 2019. pages 305-310, IEEE, 2019. [doi]

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