Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis

María C. Molina, Rafael Ruiz-Sautua, José M. Mendías, Román Hermida. Bit-Level Allocation for Low Power in Behavioural High-Level Synthesis. In Jorge Juan-Chico, Enrico Macii, editors, Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation, 13th International Workshop, PATMOS 2003, Torino, Italy, September 10-12, 2003, Proceedings. Volume 2799 of Lecture Notes in Computer Science, pages 617-627, Springer, 2003. [doi]