A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs

Md. Nazrul Islam Mondal, Kohan Sai, Koji Nakano, Yasuaki Ito. A Flexible-Length-Arithmetic Processor Using Embedded DSP Slices and Block RAMs in FPGAs. In Juan E. Guerrero, editor, The First International Symposium on Computing and Networking - Across Practical Development and Theoretical Research, Dogo SPA Resort, Matsuyama, Japan, December 4-6, 2013. pages 75-84, IEEE Computer Society, 2013. [doi]

Abstract

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