A 264-to-287GHz, -2.5dBm Output Power, and -92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL - researchr publication authors

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Byeong-Taek Moon, Sang-Gug Lee, Jaehyouk Choi. A 264-to-287GHz, -2.5dBm Output Power, and -92dBc/Hz 1MHz-Phase-Noise CMOS Signal Source Adopting a 75fsrms Jitter D-Band Cascaded Sub-Sampling PLL. In IEEE International Solid- State Circuits Conference, ISSCC 2023, San Francisco, CA, USA, February 19-23, 2023. pages 364-365, IEEE, 2023. [doi]

This author has not been identified. Look up 'Byeong-Taek Moon' in GoogleThis author has not been identified. Look up 'Sang-Gug Lee' in GoogleThis author has not been identified. Look up 'Jaehyouk Choi' in Google

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