Ludovic Moreau, Rémi Dekimpe, David Bol. A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells. In IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019. pages 1-4, IEEE, 2019. [doi]
@inproceedings{MoreauDB19,
title = {A 0.4V 0.5fJ/cycle TSPC Flip-Flop in 65nm LP CMOS with Retention Mode Controlled by Clock-Gating Cells},
author = {Ludovic Moreau and Rémi Dekimpe and David Bol},
year = {2019},
doi = {10.1109/ISCAS.2019.8702680},
url = {https://doi.org/10.1109/ISCAS.2019.8702680},
researchr = {https://researchr.org/publication/MoreauDB19},
cites = {0},
citedby = {0},
pages = {1-4},
booktitle = {IEEE International Symposium on Circuits and Systems, ISCAS 2019, Sapporo, Japan, May 26-29, 2019},
publisher = {IEEE},
isbn = {978-1-7281-0397-6},
}