Katell Morin-Allory, Laurent Fesquet, Dominique Borrione. Asynchronous Assertion Monitors for multi-Clock Domain System Verification. In 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 14-16 June 2006, Chania, Crete, Greece. pages 98-102, IEEE Computer Society, 2006. [doi]
@inproceedings{Morin-AlloryFB06, title = {Asynchronous Assertion Monitors for multi-Clock Domain System Verification}, author = {Katell Morin-Allory and Laurent Fesquet and Dominique Borrione}, year = {2006}, doi = {10.1109/RSP.2006.9}, url = {http://doi.ieeecomputersociety.org/10.1109/RSP.2006.9}, researchr = {https://researchr.org/publication/Morin-AlloryFB06}, cites = {0}, citedby = {0}, pages = {98-102}, booktitle = {17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 14-16 June 2006, Chania, Crete, Greece}, publisher = {IEEE Computer Society}, isbn = {0-7695-2580-6}, }