Marzieh Morshedzadeh Morshedzadeh, Ali Jahanian. Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage. In Erik Brunvard, Ken Stevens, Joseph R. Cavallaro, Tong Zhang 0002, editors, Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake Cit, UT, USA, May 3-4, 2012. pages 303-306, ACM, 2012. [doi]
@inproceedings{MorshedzadehJ12,
title = {Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage},
author = {Marzieh Morshedzadeh Morshedzadeh and Ali Jahanian},
year = {2012},
doi = {10.1145/2206781.2206855},
url = {http://doi.acm.org/10.1145/2206781.2206855},
researchr = {https://researchr.org/publication/MorshedzadehJ12},
cites = {0},
citedby = {0},
pages = {303-306},
booktitle = {Great Lakes Symposium on VLSI 2012, GLSVLSI'12, Salt Lake Cit, UT, USA, May 3-4, 2012},
editor = {Erik Brunvard and Ken Stevens and Joseph R. Cavallaro and Tong Zhang 0002},
publisher = {ACM},
isbn = {978-1-4503-1244-8},
}